How to create a programmable clock in RTL(Verilog)

It really depends on what you mean by "manageable jitter". Except on frequencies that are a divisor of the original frequency (500MHz), you will have a jitter of about one original clock period (2ns). If you need a lower jitter, you must either use the FPGA's reconfigurable plls (but you will be more limited in the available frequencies) or use an external DDS.

You can reduce the impact of glitches by adding a register stage on the output, clocked by the 500MHz clock.

I am not sure but I think that on a Stratix you can connect a generated signal to the global clock network, either directly or through a clock control block. I just now this isn't possible on the Cyclone family.