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A more generic way would be to use two integers, a and b, with b > a. Then the algorithm would be (in pseudo code):
on each clock cycle:
if (accumulator > b-a)
accumulator = accumulator + a - b
generate a pulse on clock output
else
accumulator = accumulator + a
end if
This will generate a pulse with a frequency of Fsys * a / b
If instead of a pulse you change the sign of the output, it will generate a rectangular signal with a duty cycle as close as 50% as you can get, with a frequency of Fsys * a / (2*b)
Be careful if you plan to use this generated signal as a clock inside the FPGA itself, as you could have problems with glitches.
[daven....I intended to use the generated clock as the real clock signal inside the FPGA! The frequency resolution does not have to be fine at 1 HZ ( can be in KHz) as along as the clock can be used to clock logics....Thanks again...daven]
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