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This is simply impossible with a digital clock generator.
Besides the 1 Hz frequency resolution, a jitter specification is necessary to decide about possible solutions. In general, the mentioned parameters demand for an analog PLL with low reference frrequency, not feasible with FPGA built-in PLLs.
[...Thank you for your prompt response, 1 Hz frequency step is my wish. In my design, I really need the 500 MHz as the master clock and the slower generated clock (x Hz - 200 MHz) to be synchronous with the 500 MHz. The slower generated clock is the real clock that will be used to drive logics inside the Stratix III FPGA so clock jitter needs to be manageable. The frequency step can be in KHz (course) if necessary for trade off with better jitter and synchronous clock. I have also tried to use the Mega Wizard to PLL to output 1 clock at 500 MHz and the 2nd output at 200 MHz but these two don't sync up. Any help will be appreciate it....Thank you, DN ]
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