How to create a programmable clock in RTL(Verilog)

A more generic way would be to use two integers, a and b, with b > a. Then the algorithm would be (in pseudo code):

on each clock cycle:

if (accumulator > b-a)

accumulator = accumulator + a - b

generate a pulse on clock output

else

accumulator = accumulator + a

end if

This will generate a pulse with a frequency of Fsys * a / b

If instead of a pulse you change the sign of the output, it will generate a rectangular signal with a duty cycle as close as 50% as you can get, with a frequency of Fsys * a / (2*b)

Be careful if you plan to use this generated signal as a clock inside the FPGA itself, as you could have problems with glitches.