How to constrain a clock coming from HPS as input clock to FPGA?

Is your board already designed or can you still make changes? If that's a possibility and you have slow I/O like push buttons, LEDs, etc... on the FPGA side of the device perhaps you can wire them up to the HPS I/O to free up a clock pin. I assume you want the FPGA PLL because you have multiple frequencies or need a higher frequency than what the HPS can provide to the FPGA? If not then you could drive everything off that same clock but I'm guessing you have your reasons for wanting a FPGA PLL.

When you daisy chain PLLs you have to make sure the jitter from the first PLL doesn't exceed the jitter tolerance of the second PLL. So in your case you need to make sure the jitter from the HPS PLL is low enough that the PLL in the FPGA doesn't loose lock. So if you can move a pin I would recommend do that since chasing PLL issues is not fun.