How to constrain a clock coming from HPS as input clock to FPGA?

One more thing, are you driving the HPS 25MHz clock into a PLL in the FPGA fabric? I highly advise against that because you'll need to perform jitter analysis to ensure the FPGA PLL will remain stable. PLLs loose lock if the input clock jitter exceeds the tolerance of the PLL so feeding a PLL output from the HPS (which will have clock jitter) into a FPGA PLL input could be problematic. When a PLL looses lock then the PLL output clocks will become unstable and can lead to functional failures in the hardware. It would be less problematic to drive a common clock into the FPGA that drives PLLs in the HPS as well as the HPS PLL inputs, but this also means that the FPGA must be configured first before the HPS boots.