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Altera_Forum
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11 years ago

How to constrain a clock coming from HPS as input clock to FPGA?

Hi I am Using Cyclone V SoC 5CSXFC6C6U23I7. to build the system I have used HPS output clock for FPGA. so there is no clock PIN I have used in My design from FPGA side. Hence I am unable to ap...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Looks like this issue is fixed in 14.1 I added a 100Mhz user0 clock to the GHRD and this was in the FPGA interfaces .sdc file:

create_clock -period 10.0 [get_pins -compatibility_mode *|fpga_interfaces|clocks_resets|h2f_user0_clk]

So I think all you need to do is create/add this constraint in your own user constraints file:

create_clock -period 40.0 [get_pins -compatibility_mode *|fpga_interfaces|clocks_resets|h2f_user0_clk]