How to constrain a clock coming from HPS as input clock to FPGA?

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Which version of Quartus are you using and which user clock are you exposing to the FPGA fabric? I thought these were automatically constrained but it doesn't sound like that's the case after all.

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Quartus II 64 bit Version 14.0.2 Build 209 09/17/2014 SJ Full version

I am using "HPS-to-FPGA user 0 clock" with frequency 25 Mhz for FPGA fabric

It is input to pll with name SubClk as shown below and several outputs are taken from PLL

alteraplliiop alteraplliiop // Altera's PLL macro

(

// Outputs

.locked (PllLock)

, .outclk_0 (Clk125) // 125MHz

, .outclk_1 (Clk625) // 62.5MHz (IBCMCLK)

, .outclk_2 (RxClk625) // 62.5MHz

, .outclk_3 () // 100MHz (Not use)

, .outclk_4 (Clk25) // 25MHz

, .outclk_5 () // 15.625MHz (Not use)

// Inputs

, .refclk (SubClk) // Refclk 25MHz

, .rst (~nPllReset) // Reset

);

Total logic utilization is 66%.

If you need some more information related to it them please ask me because there are lot of timing violation