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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to connect to standard components with Avalon-ST signals?

Hello,

After writing a VHDL file and creating a wrapper for this design in Qsys, I get errors connecting the component to an Avalon-ST data bus.

The messages are about missing ready, valid, startofpacket and endofpacket signals.

If I create I/O for these signals than I get extra ports visible for my component in Qsys, but other components from the standard library don’t have visible I/O for the controlling signals.

Is there a manual/tutorial how to connect to standard components with Avalon-ST busses?

The “Avalon Steaming Interfaces” gives only information about the signals but not how to connect your own design to it.

Best regards,

Johan Palmen

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Those signals are optional, but when you connect a stream to a source, they both need to have the same set of signals. i.e. if one of them has the start/end of packet signals, the other one must have them too.

    Some of the components in QSys can be configured to enable of disable those signals (it is usually called 'packets support').

    To help you further we would need a more precise description of what you are trying to do and the exact error messages you get.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I'm trying to use the "FIR filter 2D" in the example project "vip_example_design_3c120" for the Cyclone III starter kit.

    The RGB data has a width of 24-bit, the "FIR filter 2D" has a maximum width of 20-bit.

    I tried to split the signal into R, G and B (3x 8-bit), using three FIR 2D filters and then merge the 3x 8-bit signals into one 24-bit RGB-signal.

    By following the online course "Custom Components for SOPC Builder (Legacy Course)" I was able to create the "ready" and "valid" signals for my component. These signals don't show up as regular in- and outputs, contrary to my earlier attempt. (So this part of my problem is solved.)

    After connecting my new component to another component with a RGB-signal I got the following message: "The source has a startofpacket signal of 1 bits, but the sink does not"

    The same goes for the endofpacket signal.

    Best regards,

    Johan Palmen
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You will have to include the start and end of packet signals too and connect them through.