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Altera_Forum
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14 years ago

How to connect to standard components with Avalon-ST signals?

Hello, After writing a VHDL file and creating a wrapper for this design in Qsys, I get errors connecting the component to an Avalon-ST data bus. The messages are about missing ready, valid, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Those signals are optional, but when you connect a stream to a source, they both need to have the same set of signals. i.e. if one of them has the start/end of packet signals, the other one must have them too.

Some of the components in QSys can be configured to enable of disable those signals (it is usually called 'packets support').

To help you further we would need a more precise description of what you are trying to do and the exact error messages you get.