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Altera_Forum
Honored Contributor
Honored ContributorHow to connect to standard components with Avalon-ST signals?
Hello, After writing a VHDL file and creating a wrapper for this design in Qsys, I get errors connecting the component to an Avalon-ST data bus. The messages are about missing ready, valid, ...
Altera_ForumHonored Contributor
Honored ContributorYou will have to include the start and end of packet signals too and connect them through.
