How to connect more than one FPGA-board

Hi,

they can comunicate to each other over the PCIe bus.

Since the DE4 has a 4x PCIe 2.0 interface, you can get 4x 5 Gbit/s full duplex for each DE4, assuming the motherboard supports it.

It's also possible to use the HSMC connector. You'll need to find or design a cable or PCB with suitable pinouts to interconnect two DE4s.

Maybe SAMTEC has suitable assemblies.

http://www.samtec.com/flex_circuitry/flex_standard_hs.aspx?s=cafc

In terms of software and design, there's no support for managing more than one FGPA.

Of course, Altera provides multiple comunication blocks (PCIe, SeriaLite, ALT_LVDS, etc) that you can and should use but beyond that, you're on your own.

You can use Samtec cables for connecting boards via the HSMC connectors, however, I would not recommend it. I have the cables, and there is no mechanical retention mechanism on the cable, so in my opinion it would not be very reliable in a system.

You could connect multiple boards via their PCIe interfaces. I have a board from OneStopSystems;

http://www.onestopsystems.com/pcie_atx_bp.php

that I plan on using for testing a couple of Stratix IV GX development kits. The board connects to the PCI-Express card on my laptop. A nice convenient setup.

What are your data flow requirements? Where is the data coming from? Are you talking MB/s, GB/s, TB/s? Or is the task 'processing' dominated?

Do your FPGAs need to be reconfigured dynamically, or can they be configured once at power-on? This is a critical question, as reconfiguring a device on the PCIe bus would likely require re-enumeration of the PCIe buses, and hence, you'd want to make sure all the software was in place on the host to support that.

There is no support for connecting Quartus to multiple boards, other than to use multiple byte-blasters. In my systems, a control processor (PowerPC) and system controller (FPGA) are always powered, and the data processing FPGAs are powered on/off and reconfigured dynamically under software control, eg.,

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

Cheers,

Dave

Thanks guys, much appreciated!

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... they can comunicate to each other over the PCIe bus.

Since the DE4 has a 4x PCIe 2.0 interface, you can get 4x 5 Gbit/s full duplex for each DE4, assuming the motherboard supports it...

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Great. It seems PCIe is the way to go.

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...What are your data flow requirements? Where is the data coming from? Are you talking MB/s, GB/s, TB/s? Or is the task 'processing' dominated?...

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That is a very good question. I forgot to specify that. :oops:

The data will be collected from the network ports on each card ( approx 50% of 1GBps capacity in use per port).

At least 2 Network-ports on each preprocessing-card will be in use.

So up to 2x0.5GBps=1GBps of data. The preprocessing of data ( on the inputcards ) could probably double that number.

Thus, worstcase we're talking 2GBps of traffic per card to the main processing card. Numbers might change, but we're talking GBps speeds for sure.

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Do your FPGAs need to be reconfigured dynamically, or can they be configured once at power-on?

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Cards does not need to be reconfigured dynamically.

Solution will be uploaded to the cards at power-on.

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There is no support for connecting Quartus to multiple boards, other than to use multiple byte-blasters.

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So basically the communication has to be handled on a per-boardlevel basis. Fair enough.

I suppose the trick is to delve deeper into documentation of PCIe communication with the Altera board(s).

Any pointers towards good places to start? The altera documentation obviously, but if there are any other/specific sources of information you would reccomend, I'd appreciate the gesture.

Best Regards

A.

Hi,

well, obviously, the PCIe Compiler documentation is one place to start.

http://www.altera.com/products/ip/iup/pci-express/m-alt-pcie8.html

Some generic information about PCIe, assuming you're not very familiar with it.

PCIe, basically, behaves as a good old PCI: a master/slave memory mapped interface where devices card be either masters, slaves or, most often, both.

Each slave device will present itself as a "memory like" range of addresses. This range will be whatever you wish. You can even expose the in-FPGA and on-card RAM through this range.

Masters will request read/writes from a given address range.

So, you'll need to implement suitable PCIe designs in your cards.

One solution is to have your data gather cards be just slaves and make your main card be the master. But you can implement whatever suits you best.

Now, before the master card can address the slaves, it needs to be told their address. You'll need to write a small software driver for that.

I suggest you start by using Jungo's WinDriver in trial mode.

http://www.jungo.com/st/windriver_usb_pci_driver_development_software.html

You may (or not) also want to use the driver to help manage the flow of data from the slaves to the master.

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... worstcase we're talking 2GBps of traffic per card to the main processing card. Numbers might change, but we're talking GBps speeds for sure.

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No board-to-board communications? Just board-to-host?

Cards does not need to be reconfigured dynamically.

Solution will be uploaded to the cards at power-on.

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Then the DE4 will work fine for that.

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Any pointers towards good places to start? The altera documentation obviously, but if there are any other/specific sources of information you would reccomend, I'd appreciate the gesture.

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What OS are you planning on using on the host and on the boards (if any)?

My current generation of hardware is housed in compactPCI crates. Each board has a PowerPC interface running Linux. Each crate has an x86 host CPU. The host CPU runs a virtual network driver that turns the PCI connection between host-and-peripheral boards into a network connection. The system is 120 boards housed in 8 crates. The main data flow is control system commands down to all the boards, and data coming back up. There is no need for board-to-board communication, but the network does allow it. This scheme requires an OS at either end, since you are pushing/putting network packets into the OS network stack.

On my older generation of boards. There is a DSP for local control, and its not powerful enough to implement a network stack. In that case, the host CPU programs the DMA controller on each board (a PLX PCI9054 PCI bridge) to move data between the boards and host memory. You could conceivably do something similar if you were not going to have much intelligence on your processing board, i.e., no network stack.

I have not tried accessing my Stratix IV GX kits yet over PCIe. I had expected to be able to play with the default sysfs nodes that get created for each PCI device. These nodes allow you to perform read/write accesses to PCI memory spaces. I'd recommend starting with that method, and blinking an LED :)

Cheers,

Dave