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Honored Contributor
Honored Contributorhow to connect fpll output to transceiver transmit clock
My design is such that I will require all transceiver channels to be full duplex(both transmit and receive). I have instantiated a PCIexpress module with uses one of the channels as a global PLL for ...
Altera_ForumHonored Contributor
Honored ContributorHi, just wonder which IP core that you are using to instantiate the PCIe module? My understanding with PCIe IP core is generally limited by the option provided by the IP ie which TX PLL to use. You might need to explore using Native PHY if you want to use fPLL as TX PLL. However, you might need to build all the other required PCIe logics if you are using Native PHY.
