How to configure PCIe Map Address and PCIe IP Compiler in Qsys

Hi Everyone,

I have had some problems when a try to configure the parameters of IP compiler for PCIe. The main idea of applicaction is access the Inputs, Outputs and Input_CSR of 64 FIFOS inside Qsys using PCIe.

The configuration is:

BAR_0 => 64 Fifos_IN, where I configured the map address from 0x00000020 till 0x00001300 (Fifo1_IN => 0x00000020; Fifo2_IN=>0x00000030; Fifo3_IN=>0x00000040;...)

BAR_2 => 64 Fifos_In CSR, where I configured the map address from 0x00000000 till 0x00000800 (Fifo1_In CSR => 0x00000000 - 0x0000001f; Fifo2_In CSR => 0x00000020 - 0x0000003f;...)

BAR2_2 => 64 Fifos_Out, where I configured the map addredd from 0x000001000 till 0x00001660 (Fifo1_Out => 0x00001000; Fifo2_IN=>0x00001010; Fifo3_IN=>0x00001020;...)

BAR_0 => 64 Bit prefetchable

Bar_2 => 32 Bit Not-prefetchable

I have done a lot of test with diferent number of fifos inside Qsys. For example, when I try compile just 8 fifos inside Qsys, I don't have problem and I can write in all fifos and read the CSR parameters. However, when I try put more fifos inside Qsys, the host application that i use to access the PCIe simply stop work, and I have to reboot my PC.

I think the problem is the configuration of PCI IP Compiler, I don't know how to set the right parameters such as "Number of address page" and "Size of page Address". I don't know the relationship beetween this parameters and the amount of blocks that I can connect in PCIe's BARs.

I have tried a lot of combinations of "Number of address page" and "Size of page Address" and with each combination, I have problem with a different number of fifos configured inside Qsys.

Please, i really appreciate if somebode could help with this parameters ("Number of address page" and "Size of page Address"). I have tried read a the IP Compiler for PCI User Guide, but I couldn't understand how this parameters works.

Thanks for helping