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Altera_Forum
Honored Contributor
Honored Contributorhow to calculate the board clock skew
hi,
I try to calculate delay value for set_input_delay constraint using the rule below: input delay (max) = Board Delay (max) - Board clock skew (min) + Tco(max) = Tdata_PCB(max) + Tco(max) - (Tclk2ext(min) - Tclk1(max)) input delay (min) = Board Delay (min) - Board clock skew (max) + Tco(min) = Tdata_PCB(min) + Tco(min) - (Tclk2ext(max) - Tclk1(min)) I can get the Tco(max) and Tco(min) from the ASSP's datasheet, so there is no problem with them. Then I saw a example provided by altera shows that there are no Tdata_PCB(max) and Tdata_PCB(min), but just one value---Tdata_PCB. I think I can calculate it by 1ns/15cm. but when I turn to board clock skew, the example uses two values: 0.5 for Tskew(max) and -0.5 for Tskew(min). so my question is how to calculate/determine the board clock skew(max/min)?:confused: thanks yibin :)5 Replies
Altera_Forumhi, ashishkaps, thanks for sharing your experience! the method you mentioned has a limitation and I got it.
At the same time, the way to calculate the skew still make me confused. According to Rsyc's word, can I use a ondoscope to probe the clock port of ASSP and FPGA and figure out the difference? or is there a example to show the process how the skew turn to a exact value? thanks!- Altera_Forum
Hi...i appreciate your response to my post..but the thing is my method is for beginners and yes it will work for some cases..
but for complex cases you will have to follow what RYSC has said..because we wont be facing idealistic situations in synthesis.. currently i am synthesis a module in which these ideas fail badly..because the timing is pretty complex.. Actually you should know what you are trying to constrain..specially the clock skew is the heart of constraining.. Yes with experience you will get hold of it...good luck - Altera_Forum
hi, rysc, i know that the clock skew can not be avoided completely and as you said, that's what it's showing. but how can i get this value(+/- 0.5ns in the example)? by ondoscope or something else (tool or formula)?:oops:
the way ashishkaps provided seems to be a good method to workaround?;)
thanks!
- Altera_Forum
I seldom see users have max and min values for PCB delays, they usually just have one value. Sometimes they deviate from that by adding/subtracting a bit to get max min, but I don't have a good rule of thumb. It is small though.
In the example you posted, the skew number is for the clock, which is feeding two different devices. So it's not the max/min of a single trace delay(like the data), but two physically different clock routes, which are more likely to have some skew. Yes, layout tries to minimize clock skew, but that's what it's showing and hence why it's a larger number. - Altera_Forum
well bro i too am struggling with the same idea..
but i am taking set_input_delay max as 70% of clock period and ouput delay max as 30% of clock.. in worst case you can use 60-40 ratio.. this is not the exact logic...but this is what i know...:(
