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Altera_Forum
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14 years ago

how to calculate the board clock skew

hi, I try to calculate delay value for set_input_delay constraint using the rule below: input delay (max) = Board Delay (max) - Board clock skew (min) + Tco(max) = Tdata_PCB(max) + Tco(max)...
Altera_Forum's avatar
Altera_Forum
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14 years ago

hi, ashishkaps, thanks for sharing your experience! the method you mentioned has a limitation and I got it.

At the same time, the way to calculate the skew still make me confused. According to Rsyc's word, can I use a ondoscope to probe the clock port of ASSP and FPGA and figure out the difference?

or is there a example to show the process how the skew turn to a exact value?

thanks!