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Altera_Forum
Honored Contributor
Honored Contributorhow to calculate the board clock skew
hi, I try to calculate delay value for set_input_delay constraint using the rule below: input delay (max) = Board Delay (max) - Board clock skew (min) + Tco(max) = Tdata_PCB(max) + Tco(max)...
Altera_ForumHonored Contributor
Honored ContributorHi...i appreciate your response to my post..but the thing is my method is for beginners and yes it will work for some cases..
but for complex cases you will have to follow what RYSC has said..because we wont be facing idealistic situations in synthesis.. currently i am synthesis a module in which these ideas fail badly..because the timing is pretty complex.. Actually you should know what you are trying to constrain..specially the clock skew is the heart of constraining.. Yes with experience you will get hold of it...good luck
