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Altera_Forum
Honored Contributor
Honored Contributorhow to calculate the board clock skew
hi, I try to calculate delay value for set_input_delay constraint using the rule below: input delay (max) = Board Delay (max) - Board clock skew (min) + Tco(max) = Tdata_PCB(max) + Tco(max)...
Altera_ForumHonored Contributor
Honored ContributorI seldom see users have max and min values for PCB delays, they usually just have one value. Sometimes they deviate from that by adding/subtracting a bit to get max min, but I don't have a good rule of thumb. It is small though.
In the example you posted, the skew number is for the clock, which is feeding two different devices. So it's not the max/min of a single trace delay(like the data), but two physically different clock routes, which are more likely to have some skew. Yes, layout tries to minimize clock skew, but that's what it's showing and hence why it's a larger number.
