How to build a memory?

Hi , I have to write VHDL code of a memory.

the function is :

there just 2 states,read and write.

if we=1 , the data are wrote into the memory, otherwise it always shows read state ,that means the data_out shows the data which are stored in the memory.

There are 5 inputs:

clock, enable, write(we), data_in (width of d bit),address (width of c bit)

and one output :

data_out (width of d bit)

I have to use lots of same unit of single memory cell which can only save 1 bit (I was told to use RS-flip flop but I don’t know how) and unit demux to build the whole memory. That means use separate demux, single-cell memory entities etc.

Without use ram block which already in FPGA existed.

Does anyone can help me or give me some ideas?