How to build a carry-chain in Quartus II fitter instead of using LUTs?

Hello everyone,

I have a question about using Quartus II fitter to build a carry-chain. Specifically, I want to ensure that the fitter uses a real adder circuit instead of using LUTs during the layout process.

Here is my verilog:

module Tfine_IP3(input clk_50M,
input start,
output clk,
output Sample_clk,
output clk_trig,
output [282:0]th_code/*synthesis keep*/);
wire [282:0]cout;
wire [282:0]w;

add a0(.dataa(1'b1),.datab(1'b0),.cin(start),.result(th_code[0]),.cout(cout[0]));

add a1(.dataa(1'b1),.datab(1'b0),.cin(cout[0]),.result(th_code[1]),.cout(cout[1]));
add a2(.dataa(1'b1),.datab(1'b0),.cin(cout[1]),.result(th_code[2]),.cout(cout[2]));
add a3(.dataa(1'b1),.datab(1'b0),.cin(cout[2]),.result(th_code[3]),.cout(cout[3]));
endmodule

adder settings

RTL viewer (implement by carry-chain):

Technology map viewer(implement by LUT):

I have been trying to find a way to force the Quartus II fitter to use an adder circuit during layout, but have not had much success. I searched advanced setting(Fitter) for a long time but to find a proper way to implement the carry-chain. Can anyone provide me with some guidance or tips on how to accomplish this?

I am using Quartus II version [quartus ii 18.1 lite edition], and any help would be greatly appreciated.

Thank you in advance!