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kgrcfff
New Contributor
New ContributorHow to build a carry-chain in Quartus II fitter instead of using LUTs?
Hello everyone,
I have a question about using Quartus II fitter to build a carry-chain. Specifically, I want to ensure that the fitter uses a real adder circuit instead of using LUTs during the ...
Hi,
In the verilog code, I think you have to connect dataa and datab to input ports instead of constant 1'b1 / 1'b0. If connect to input ports you'll get map viewer result like below pic:
For example, taking single lpm_add_sub megafunction original map viewer result, the result like pic below:
If connect lpm_add_sub megafunction dataa and datab to constant, you'll get the result like below pic instead:
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
FvM
Super Contributor
Super ContributorHello,
I think there are two problems with your experimental code.
1. lpm_add_sub is an adder macro, not a LAB low-level primitive. It's processed as input to the synthesis tool, not directly inferring logic array blocks.
2. By feeding all adder inputs except carry with constants, Quartus will be most certainly blocked from using arithmetic mode and not use carry chain.
I wonder what you want to achieve with the design? Create a delay line?
The best way to make Quartus use the carry chain is to design a problem that is recognized as arithmetic.
Regards,
Frank
I think there are two problems with your experimental code.
1. lpm_add_sub is an adder macro, not a LAB low-level primitive. It's processed as input to the synthesis tool, not directly inferring logic array blocks.
2. By feeding all adder inputs except carry with constants, Quartus will be most certainly blocked from using arithmetic mode and not use carry chain.
I wonder what you want to achieve with the design? Create a delay line?
The best way to make Quartus use the carry chain is to design a problem that is recognized as arithmetic.
Regards,
Frank
