how to achieve 4 channel LVDS ADC read

Question

Hello,

ADC: TI  ADC3422 , 4 channel 12 bit ADC with 50M sample rate, LVDS
FPGA: Intel EP4CE15M9I7N
To read this ADC, so the clock should be as fast as 150MHz at rising and falling edge.
Is there any special IP as DDR RAM ALTPHY required?
Can EP4CE15M9I7N support four channels LVDS up to 150MHz read?

engwei_o_intel · Accepted Answer

Hi there

Since the LVDS support up to deserialization factor of 10, you can refer to link below to compute for other factors:
https://www.youtube.com/watch?v=02lgfcxSjQA

For the spec you mentioned, Cyclone IV shall be supported.

Thanks.

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how to achieve 4 channel LVDS ADC read

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