Forum Discussion
Occasional ContributorHow set timing constraint for such clock
In my design, the spi clock to external device was divided by counter.
if use below to set timing constraint, it reports below warning:
Node: nios:nios_0|mcu_uadc:mcu_uadc_0|read_cnt[2] was determined to be a clock but was found without an associated clock assignment.
No paths exist between clock target "uadc_sclk" of clock "uadc_sclk" and its clock source. Assuming zero source clock latency.
So, what should I do to set timing constraints?
always @(negedge clk or negedge reset_n) begin
if(reset_n == 1'b0)
write_cnt <= 8'd0;
else if(spi_current_state == SPI_STATE_WRITE)
write_cnt <= write_cnt + 8'd1;
else
write_cnt <= 8'd0;
end
always @(negedge clk or negedge reset_n) begin
if(reset_n == 1'b0)
read_cnt <= 8'd0;
else if(spi_current_state == SPI_STATE_READ)
read_cnt <= read_cnt + 8'd1;
else
read_cnt <= 8'd0;
end
assign uadc_sclk = (write_cnt[7:3] >= 5'd4 && write_cnt[7:3] <= 5'd27 && write_cnt[2:0] <= 3'd3)? 1'b1 :
(read_cnt[7:3] >= 5'd4 && read_cnt[7:3] <= 5'd27 && read_cnt[2:0] <= 3'd3)? 1'b1 : 1'b0;
First, I would make uadc_sclk be a reg variable and not a wire.
Then, you have to add timing constraints for your derived clocks. For example, I have this in my .sdc file for a design:
# Input 50MHz reference clock create_clock -period 20.0 -name CLOCK_50 [get_ports {CLOCK_50}] # Created clocks based on PLLs (CPUCLK = 80MHz) create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50 -name CPUCLK {pll|altpll_component|pll|clk[0]} # Created clocks based on logic (RTCCLK = 25KHz) create_generated_clock -source {pll|altpll_component|pll|clk[0]} -divide_by 5000 -duty_cycle 50 -name RTCCLK {dk8ea_clock:rtc|rtcclk}where the clock RTCCLK is generated via this code:
// system clock divider to RTC clock rate reg rtcclk; // rtc clock reg [31:0] rtcdiv; // rtc prescale clock divisor always @(posedge clk) begin if (reset) begin rtcdiv <= #TPD 32'd0; rtcclk <= #TPD 1'b0; end else begin rtcdiv <= #TPD (rtcdiv == PRESCALE-1'd1) ? 32'd0 : rtcdiv+1'd1; if (rtcdiv == 32'd1) rtcclk <= #TPD ~rtcclk; end end
8 Replies
ak6dnRegular Contributor
First, I would make uadc_sclk be a reg variable and not a wire.
Then, you have to add timing constraints for your derived clocks. For example, I have this in my .sdc file for a design:
# Input 50MHz reference clock create_clock -period 20.0 -name CLOCK_50 [get_ports {CLOCK_50}] # Created clocks based on PLLs (CPUCLK = 80MHz) create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50 -name CPUCLK {pll|altpll_component|pll|clk[0]} # Created clocks based on logic (RTCCLK = 25KHz) create_generated_clock -source {pll|altpll_component|pll|clk[0]} -divide_by 5000 -duty_cycle 50 -name RTCCLK {dk8ea_clock:rtc|rtcclk}where the clock RTCCLK is generated via this code:
// system clock divider to RTC clock rate reg rtcclk; // rtc clock reg [31:0] rtcdiv; // rtc prescale clock divisor always @(posedge clk) begin if (reset) begin rtcdiv <= #TPD 32'd0; rtcclk <= #TPD 1'b0; end else begin rtcdiv <= #TPD (rtcdiv == PRESCALE-1'd1) ? 32'd0 : rtcdiv+1'd1; if (rtcdiv == 32'd1) rtcclk <= #TPD ~rtcclk; end end
XQSHENwhat make difference here?
- ak6dn
What is your question? I do not understand what you are asking.
- SyafieqS
Super Contributor
Hi,
"Node: nios:nios_0|mcu_uadc:mcu_uadc_0|read_cnt[2] was determined to be a clock but was found without an associated clock assignment"
Seem like above error can be caused in two ways:
1) A clock assignment was determined to be invalid, so its source objects no longer have a clock associated with them.
2) When analyzing the netlist, the node was found feeding a clock port with no other clocks feeding it.
You can use the derive_clocks command to automatically find all clock nodes in the design. Also, for any clocks that were ignored, review the warning or error message associated with the command to prevent the clock from being ignored.
Once all the node with unassociated clocks are identified, you should apply you timing constraint for derived clock e.g. create_generated_clock
Hope that helps.
- XQSHEN
Thanks a lot!
- SyafieqS
Let me know if there is any update or concern on this.
- XQSHEN
No, you can close it.
- SyafieqS
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
