How set timing constraint for such clock

First, I would make uadc_sclk be a reg variable and not a wire.

Then, you have to add timing constraints for your derived clocks. For example, I have this in my .sdc file for a design:

# Input 50MHz reference clock

create_clock -period 20.0 -name CLOCK_50 [get_ports {CLOCK_50}]

# Created clocks based on PLLs (CPUCLK = 80MHz)

create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50 -name CPUCLK {pll|altpll_component|pll|clk[0]}

# Created clocks based on logic (RTCCLK = 25KHz)

create_generated_clock -source {pll|altpll_component|pll|clk[0]} -divide_by 5000 -duty_cycle 50 -name RTCCLK {dk8ea_clock:rtc|rtcclk}

where the clock RTCCLK is generated via this code:

    // system clock divider to RTC clock rate

    reg           rtcclk;       // rtc clock
    reg [31:0]    rtcdiv;       // rtc prescale clock divisor

    always @(posedge clk)
	begin
	if (reset)
	    begin
	    rtcdiv <= #TPD 32'd0;
	    rtcclk <= #TPD 1'b0;
	    end
	else
	    begin
	    rtcdiv <= #TPD (rtcdiv == PRESCALE-1'd1) ? 32'd0 : rtcdiv+1'd1;
	    if (rtcdiv == 32'd1) rtcclk <= #TPD ~rtcclk;
	    end
	end