How Many LEs will my Design Take Up

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Hello,

I apologize in advance if this has been answered before, but I am not sure what keywords to search for. I have implemented a design in Quartus, which will be programmed to a Cyclone III EP3C120F780 FPGA (I do not have the FPGA yet).

My question is this: how can I determine the size of my design? By "size", I mean the number of Logic Elements (LEs) that will be consumed by my design when it is written to the FPGA.

Hopefully, Quartus has some kind of feature that provides this information. Any help or direction will be much appreciated, as I have been asked to provide this information in a report later today.

- Bill

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Hi Bill,

you will find all your requested information in the report files after a successful Quartus run.

Kind regards

GPK

GPK,

Thank you for your reply. I believe I found the information I was looking for (copied below). Unfortunately, I'm very new to FPGAs, and I'm not entirely sure what the numbers mean. According to the manual, my device has ~45K LEs available. None of these numbers are out of 45K. Should I just multiply 0.18 x 45000 to determine the number of LEs my design is occupying?

Logic Utiliization (18%)

Combinational ALUTs (6955/38000)

Memory ALUTs (0/19000)

Dedicated Logic Registers (1177/38000)

Total Registers (1177)

Total Pins (450/488)

Total Virtual Pins (0)

Total block Memory Bits (548864/1880064)

DSP Block 18-bit elements (212/216)

Total PLLs (0/4)

Total DLLs (0/4)

Thank you,

Bill

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GPK,

Thank you for your reply. I believe I found the information I was looking for (copied below). Unfortunately, I'm very new to FPGAs, and I'm not entirely sure what the numbers mean. According to the manual, my device has ~45K LEs available. None of these numbers are out of 45K. Should I just multiply 0.18 x 45000 to determine the number of LEs my design is occupying?

Logic Utiliization (18%)

Combinational ALUTs (6955/38000)

Memory ALUTs (0/19000)

Dedicated Logic Registers (1177/38000)

Total Registers (1177)

Total Pins (450/488)

Total Virtual Pins (0)

Total block Memory Bits (548864/1880064)

DSP Block 18-bit elements (212/216)

Total PLLs (0/4)

Total DLLs (0/4)

Thank you,

Bill

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Hi Bill,

I'm a little bit confused with your available pins and also with the term "ALUT". I'm quite sure the Cyclone III don't have the advanced ALM (Adaptiv Logic Module) structure. Did you choose the specific device (Cyclone III EP3C120F780) in Quartus ?

Kind regards

GPK

Oops, we switched from Stratix to Cyclone earlier in the project and I forgot to update the Quartus Device settings.

Now the compilation report makes perfect sense.

Thank you again!

- Bill