How many clock cycle latency for 32 bit Integer Multiplication in Altera Stratix V?

Hi

Since I am developing a hardware in verilog for high frequency application using Altera Stratix FPGA, and involves 32 bit integer multiplication. The application that I am designing needs the result of the multiplication in one clock cycle.

Question: Will I get the resultant product in one clock cycle?

I referred the Stratix V handbook and it says that a DSP module can handle

: One 27*27 multiplication

: Two 18*18 multiplication

: Three 9*9 multiplication

So from the above information, two 2 DSP blocks are required for parallel multiplication and subsequent summing up. But can this be done in a clock cycle

in Stratix V(Assuming that I am working at 100 - 200 MHz internal clock)

Thanks in advance

Jeebu Jacob Thomas