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Altera_Forum
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10 years ago

How many clock cycle latency for 32 bit Integer Multiplication in Altera Stratix V?

Hi Since I am developing a hardware in verilog for high frequency application using Altera Stratix FPGA, and involves 32 bit integer multiplication. The application that I am designing needs t...
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Altera_Forum
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10 years ago

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Why not write some proof of concept code and run it through timequest?

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Hi Tricky,

Thanks for the quick reply. We dont have a quartus tool to check through timequest yet. Quartus Evaluation version wont support Stratix V. We have just given order for buying the same.

Thanks again

Cheers

Jeebu