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Honored Contributor
Honored ContributorHow many clock cycle latency for 32 bit Integer Multiplication in Altera Stratix V?
Hi Since I am developing a hardware in verilog for high frequency application using Altera Stratix FPGA, and involves 32 bit integer multiplication. The application that I am designing needs t...
Altera_ForumHonored Contributor
Honored ContributorStratix V has support for one independent 32x32 multiplication using 2 cascaded DSP blocks (internally routed). Should be able to achieve 200MHz easily for one clock cycle operation.
https://www.altera.com/products/fpga/features/dsp/stratix-v-dsp-block.html
