How effectively start with VHDL programming or maybe Verilog?

So many questions, so many answers.

Its difficult to give a proper answer without a specific question.

Did you have a specific application in mind?

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So many questions, so many answers.

Its difficult to give a proper answer without a specific question.

Did you have a specific application in mind?

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No, I have nothing in my mind. I said before I am beginner and I want to learn it so how I could have any application in mind?

But I think I asked simple questions so if someone is experienced in this so he/she would answer them very easy.

Ok well Ill show you how difficult it is to answer:

1. VHDL or Verilog: They can both give the same results. Verilog is more C like, but has more pitfalls.

2. Altera and Xilinx have very similar parts and are the two main producers of FPGAs. usually, selection comes down to factors such as tool familiarity, FPGA capabilities for your application and who you currently get chips from. This is an altera forum, so the bias is probably with altera.

3. There are many many many applications. From small microcontrollers and address decoders to large real time data processors, depending on FPGA

4. They are not microcontrollers

5. For a start, large, expesive FPGAs can suck in a huge amount of data and spew it out at the same time, after having done some processing on it. The cheaper FPGAs can also suck in large amounts of data, probably at a slower speed.

So - what is your application?

As I said I have not got any application yet. I am beginner and I would like to learn. As I see its better to chose VHDL over Verilog.

I think I will start with Altera IDE and devices Cyclones.

I must learn about design process with FPGA, what should I know to start any application.

I would recommend that you choose SystemVerilog. You might want to read the following:

Is SystemVerilog Useful for FPGA Design?

http://www.sutherland-hdl.com/papers.php

There are plenty of other usefull articles there that you may benefit from.

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I would recommend that you choose SystemVerilog. You might want to read the following:

Is SystemVerilog Useful for FPGA Design?

http://www.sutherland-hdl.com/papers.php

There are plenty of other usefull articles there that you may benefit from.

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Why do you prefer Verilog over VHDL? I have noticed the most job offers require the knowledge of VHDL so I think I will stick with it. I have not so much time for both of them.

It depends on which part of the world you want to work in. I think Europe (and military worldwide?) used to prefer VHDL while America used to prefer (system)verilog, but I think those frontiers are starting to blur now.

You will soon discover that the most difficult part of learning a HDL isn't the language syntax itself, but the concepts behind RTL design and digital logic design, especially if you have a software design background. Once you have mastered a language, learning the other one is rather easy, as it's using the same concepts with just a slightly different syntax.

I never really perceived it as a USA vs europe thing - more an FPGA vs ASIC thing. ASIC verification is now all SystemVerilog, and all the design was verilog. With most asic development done in the USA this is what made people see the USA vs europe thing. Also, VHDL came out of the department for defence, hence the military love of VHDL. Many companies spin out of Military designers, and so it spread the VHDL "love".

Now, more and more FPGA companies are going with systemverilog as FPGA designs get very complex, so verification becomes a real issue. So, to garantee yourself the best prospects, it's best to go down the SV route (but having an understanding of the technology is far more important than which language to learn, as when you understand the tech, the languages are much easier).