How effectively start with VHDL programming or maybe Verilog?

I never really perceived it as a USA vs europe thing - more an FPGA vs ASIC thing. ASIC verification is now all SystemVerilog, and all the design was verilog. With most asic development done in the USA this is what made people see the USA vs europe thing. Also, VHDL came out of the department for defence, hence the military love of VHDL. Many companies spin out of Military designers, and so it spread the VHDL "love".

Now, more and more FPGA companies are going with systemverilog as FPGA designs get very complex, so verification becomes a real issue. So, to garantee yourself the best prospects, it's best to go down the SV route (but having an understanding of the technology is far more important than which language to learn, as when you understand the tech, the languages are much easier).