how does the LVDS_RX in Cyclone 3 work

does it work like DDR clock, there is data at the rising edege clock and falling edge clock?

Is this the right way to capture the data?

component LVDS_RX

port(

rx_in : in std_logic_vector( 17 downto 0 );

rx_inclock : in std_logic := '0';

rx_out : out std_logic_vector( 35 downto 0 )

);

end component;

signal regFast : std_logic_vector( 35 downto 0 );

LVDS_RX_inst : LVDS_RX port map (

rx_in => iVdata,

rx_inclock => iVclk,

rx_out => regFast

);

procFastRegDeInterleave : process ( iVclk , regFast )

begin

if ( iVclk'event and iVclk = '1' ) then

regFastBuf( 35 ) <= regFast( 35 );

regFastBuf( 33 ) <= regFast( 34 );

regFastBuf( 31 ) <= regFast( 33 );

regFastBuf( 29 ) <= regFast( 32 );

regFastBuf( 27 ) <= regFast( 31 );

regFastBuf( 25 ) <= regFast( 30 );

regFastBuf( 23 ) <= regFast( 29 );

regFastBuf( 21 ) <= regFast( 28 );

regFastBuf( 19 ) <= regFast( 27 );

regFastBuf( 17 ) <= regFast( 26 );

regFastBuf( 15 ) <= regFast( 25 );

regFastBuf( 13 ) <= regFast( 24 );

regFastBuf( 11 ) <= regFast( 23 );

regFastBuf( 9 ) <= regFast( 22 );

regFastBuf( 7 ) <= regFast( 21 );

regFastBuf( 5 ) <= regFast( 20 );

regFastBuf( 3 ) <= regFast( 19 );

regFastBuf( 1 ) <= regFast( 18 );

regFastBuf( 34 ) <= regFast( 17 );

regFastBuf( 32 ) <= regFast( 16 );

regFastBuf( 30 ) <= regFast( 15 );

regFastBuf( 28 ) <= regFast( 14 );

regFastBuf( 26 ) <= regFast( 13 );

regFastBuf( 24 ) <= regFast( 12 );

regFastBuf( 22 ) <= regFast( 11 );

regFastBuf( 20 ) <= regFast( 10 );

regFastBuf( 18 ) <= regFast( 9 );

regFastBuf( 16 ) <= regFast( 8 );

regFastBuf( 14 ) <= regFast( 7 );

regFastBuf( 12 ) <= regFast( 6 );

regFastBuf( 10 ) <= regFast( 5 );

regFastBuf( 8 ) <= regFast( 4 );

regFastBuf( 6 ) <= regFast( 3 );

regFastBuf( 4 ) <= regFast( 2 );

regFastBuf( 2 ) <= regFast( 1 );

regFastBuf( 0 ) <= regFast( 0 );

end if;

end process;