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songsong96's avatar
songsong96
Icon for New Contributor rankNew Contributor
3 years ago

How do I select an FPGA chip with a high-speed system clock available?

Our team wants to implement an FPGA system that controls DAC Resolution 1ns width. The FPGA now in use is using Cyclone V (5ceba2f23c7). The 40MHz crystal clock is received from the outside, multipl...
FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi songsong96,

I wish to follow up with you about this case. Do you have any further questions on this matter?

Please feel free to let me know if there is any concern so that we could further assist you.

Otherwise, this thread will be marked as inactive and will be transitioned to community support because there is no update received from you in a while.

Thank You.

Regards,

Fakhrul