How do I determine which I/O PLL phase a DPA receiver has locked to?

I'm working with a design that involves a 10CX220YU484E5G receiving data from four devices over LVDS interfaces. All four devices that we're receiving data from are the same part, and one crystal provides the clock to all of them. From each device, we're receiving the following 6 signals over the LVDS interface (see attached):

• Four “data” lanes

• One “valid” signal that is high when the “data” lanes are valid

• One DDR bit clock

The DDR bit clock frequency is 300 MHz, so the throughput is 600 Mbps per data lane. Two of these devices are routed to bank 2A and two of them are routed to bank 2J. Unfortunately, this means two devices have to share the I/O PLLs in bank 2A and 2J; we just don't have enough I/O PLLs for each device to have its own. In each bank, one device's "clock" is connected to the I/O PLL's dedicated clock input. As all four devices have the same crystal as their clock source, the frequency of their bit clocks are exactly the same with some random phase difference from device to device. Our plan was to use a 10-channel LVDS receiver with DPA, with the hope that the DPA could correct for that phase difference. However, when I look at the captured data, I can tell that the word alignment for the 2nd device in each bank isn’t working properly. Note that the data doesn’t include sync words or a training pattern; the only way for us to do word alignment is to use the rising edge of the “valid” signal. It makes sense that the DPA is struggling with this, as the valid signal has very few edges for the DPA to work with.

My question: is it possible for us to "look into" the LVDS SERDES IP to see which DPA phase each channel has locked to? As a workaround, I'd like to use the DPA to lock to the bitclock from each device and then provide the DPA phase which is shifted 90 degrees ahead of that to the receiver to sample the "data" and "valid".