New Contributor
Frequent ContributorHi Kyle
Let me know if you have any question regarding this topic before we proceed to close the ticket.
Thanks.
Eng Wei
New ContributorHi Eng Wei,
I have reviewed the relevant sections of the Core Fabric handbook, but they don't answer my question. Let me rephrase it. Suppose that the DPA for one channel has locked to a specific I/O PLL phase, say, 45°. I can tell that the channel is locked because rx_dpa_locked is asserted for that channel. However, how can I check which phase (in this case, the 45° phase) that channel has locked to? I am hoping to use this information to explicitly select an I/O PLL phase to sample related channels. These related channels have very few data transitions, so we can't use the DPA for them. But, they have the same clock-to-data phase relationship as the channels that we can use DPA for.
Thanks,
Kyle
Frequent ContributorHi Kyle
We can refer to Section "Initializing the LVDS SERDES IP Core in DPA Mode" in the doc below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf
In steps number 4:
Apply the DPA training pattern and allow the DPA circuit to lock.
We can refer to datasheet below, taking Arria 10 device as example, to check for DPA lock time specs which can be applied to each channel after rx_dpa_reset port is deasserted:
https://www.intel.com/content/www/us/en/programmable/documentation/mcn1413182292568.html#mcn1413273412573
Thanks.
Eng Wei
Frequent ContributorHi Kyle
Do you still face any issue with your design?
Thanks
Eng Wei
Frequent ContributorHi Kyle
We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
