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KMour's avatar
KMour
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5 years ago

How do I determine which I/O PLL phase a DPA receiver has locked to?

I'm working with a design that involves a 10CX220YU484E5G receiving data from four devices over LVDS interfaces. All four devices that we're receiving data from are the same part, and one crystal pro...
EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Kyle

Let me know if you have any question regarding this topic before we proceed to close the ticket.

Thanks.

Eng Wei

  • KMour's avatar
    KMour
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi Eng Wei,

    I have reviewed the relevant sections of the Core Fabric handbook, but they don't answer my question. Let me rephrase it. Suppose that the DPA for one channel has locked to a specific I/O PLL phase, say, 45°. I can tell that the channel is locked because rx_dpa_locked is asserted for that channel. However, how can I check which phase (in this case, the 45° phase) that channel has locked to? I am hoping to use this information to explicitly select an I/O PLL phase to sample related channels. These related channels have very few data transitions, so we can't use the DPA for them. But, they have the same clock-to-data phase relationship as the channels that we can use DPA for.

    Thanks,

    Kyle