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Altera_Forum's avatar
Altera_Forum
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16 years ago

How can I make my design smaller in a MAX3000

Hi all!

I seem to have run into some trouble with a MAX3000A Device. I had to port over some code that was created in a .bdf (with some AHDL) to VHDL. It was a pretty straight forward process and the simulation matches great.

Except that now it takes 66 registers and I only have room for 64!

I'm looking for some advice and tips to reduce this. One thing I used a lot was to remove statements from clocked processes into CSA's (while making sure my simulation was still working).

I'm looking for you guys out there who really know what you are doing. I appreciate any and all responses.

Thanks!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    "optimisation is spending 3 hours to remove only 2 registers :-) "

    Remove registers :-D LOL , remove pipelines

    Reduce counters (optimize their size, use divided clock, share counters, restrict range, restrict signals...)

    Help, assist the synthesizer by putting (). It helps a lot.

    Restructure.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    i would compare RTL Viewer of the AHDL and VHDL to see the differences and adjust the VHDL accordingly

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Good suggestion, with the RTL viewer. However to complicate the problem, I'm also working with different versions. 10 does a lot of multiplexing while 9 does a lot of "gating"

    I'm going to keep at it, but if anyone has any other suggestions, that would be great.

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It seems that I'm getting this message that takes some time and gives me some macro cells:

    Info: Promoted pin-driven signal(s) to global signal

    Info: Promoted clock signal driven by pin "clk" to global clock signal

    Does anyone know a work around for this?