Altera_Forum
Honored Contributor
18 years agoHot FPGA!
My FPGA gets really hot after configuration. I've checked my power pins, and they are all connected to the correct supplies which are all within tolerance. Any other suggestions?
My FPGA gets really hot after configuration. I've checked my power pins, and they are all connected to the correct supplies which are all within tolerance. Any other suggestions?
A common mistake I've seen is related to the Quartus Unused I/O setting which, by default, is set to 'Outputs Driving GND' and those I/O are connected (directly) to VCC on the board. Make sure that this is not the case - as this will not only increase current consumption, but also damage the I/O buffer.
Another possibility is that you have a metastability problem caused by asynchronous logic. I have seen devices heat up real fast if you are not using synchronous design practice.
You may have forgotten to pull up the TCK pin. It's really sensitive and will pick up RF noise really quickly.
Yeah, you're lucky if your unused pins are set to "Output, Driving Ground" and all that happens is that your chip gets hot. I've seen some designs where that destroys components. In general, I think it's safer to stick with "As Inputs, Tri-stated".
Cheers, -uraslackerBee Gee,
Which FPGA are you using? You can also check the current reported by the early power estimator (EPE) versus the current you measure on your board.I would check the supply voltage of your PLL's...
I concur with Karl. VCC for PLLs should be Vcore level, not VCCIO...
Yes. Follow the Operating Conditions section of the datasheet or handbook and the pin table information and that will cover the PLL VCC connections.