Hold timing fail on a 2FF synchroniser

Hi Naveen,

"wrn and clearn are asynchronous"

Seem to me it is clock domain crossing.

You can refer to link below on how to constrain CDC.

https://www.intel.com/content/www/us/en/support/programmable/articles/000080400.html

But in general if this is CDC, you do not have a set_false_path constraint between the two clock domains, if you don't want paths between them to be analyzed for setup and hold then you can use set_clock_groups which has a lower precedence. This due to the skew across the bus can be more than 1 clock period which can cause functional errors.