NShan12
Occasional Contributor
Occasional ContributorHold timing fail on a 2FF synchroniser
Hello,
I have a 2FF synchroniser for an active LOW asynchronous write signal driven by a Microcontroller. The code is as below:
PROCESS (clk, clearn)
BEGIN
IF clearn = '0' THEN
wrn_dd <= '1';
wrn_d <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
wrn_d <= wrn ;
wrn_dd <= wrn_d;
END IF;
END PROCESS;
After running full compilation Timing analyser throws a Hold timing error from node wrn_d to node wrn_dd (only in the Fast timing corner). Why is this happening and how can it be solved?
My understanding is: Clock to Q delay of a flip flop in FPGA is such that it does not cause hold violation at the next connected flip flop. If this is true then why is a hold violation occuring in this case?
