Forum Discussion
NShan12
Occasional Contributor
Occasional ContributorHold timing fail on a 2FF synchroniser
Hello,
I have a 2FF synchroniser for an active LOW asynchronous write signal driven by a Microcontroller. The code is as below:
PROCESS (clk, clearn) BEGIN IF clearn = '0' THEN wr...
sstrell
Super Contributor
Super ContributorWhat do your SDC constraints look like for the clock and the (I'm presuming) wrn input (set_input_delay)? And do you have a false path on clearn?
NShan12Hi,
I have create clock command on clk (32 MHz) and false path set on both wrn and clearn inputs.
wrn and clearn are asynchronous.
No input delay constraints exist for both these signals. Wrn is generated by external bus controller of a Microcontroller and the timing is not deterministic due to the MCU software behaviour.
wrn is driven LOW for 125 ns by the MCU and a 32 MHz FPGA clock should capture it without miss. Is Input delay still needed in this case?
