History of interconnects and throughputs

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Hi,

I was researching around the domain and I would like to ask some expert a question that Google couldn't help me with.

:)

I was trying to trace the interconnect structures and their max data rates. To the best of my knowledge,

Avalon bus came. Then the SOPC interconnect(Buffered crossbar). Then comes Qsys with a network on chip interconnect.

I'm not too sure if there was a thing such as Avalon bus. At the moment, it seems Avalon is an interface specification.

But a few old app notes pointed to an Avalon bus as well.

People came up with bus architectures for connecting IP cores. I could find an article from 2000

http://eetimes.com/electronics-news/4112809/altera-xilinx-hop-on-diverging-buses-in-soc-plans

What I would like to know:

A short history lesson on the progression of interconnect technology.

And if there are some speed comparisons anywhere or if anyone has rough figures in his head even.

Pretty sure Qsys with its NOC would be the best. But I'm not sure atm.

Thanks

Cheers

Zubair

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Do you mean interconnect within one fpga or that between several chips.

In either case it looks like a topic for fpga makers area of focus rather than fpga field users.

I just Googled "fpga interconnect technology" and hope this link may help:

http://async.org.uk/tech-reports/ncl-eece-msd-tr-2009-145.pdf

If you mean internal fpga interconnect then I don't see Avalon bus as being relevant.

Hmm. I'll try to reword my question.

My question is about the interconnect structure between IP cores within one FPGA.

According to the SOPC builder handbook, the SOPC uses a buffered crossbar to connect the IP cores.

Qsys using a network on chip style to connect IP cores.

What did people use before SOPC builder came around with its buffered crossbar interconnect?

And is there any benchmark as to how fast/better these interconnects are compared to each other? Wherever I look, I find high bandwidth low latency etc.. But no real figures..

Hope its clear.

Cheers

Zubair

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Hmm. I'll try to reword my question.

My question is about the interconnect structure between IP cores within one FPGA.

According to the SOPC builder handbook, the SOPC uses a buffered crossbar to connect the IP cores.

Qsys using a network on chip style to connect IP cores.

What did people use before SOPC builder came around with its buffered crossbar interconnect?

And is there any benchmark as to how fast/better these interconnects are compared to each other? Wherever I look, I find high bandwidth low latency etc.. But no real figures..

Hope its clear.

Cheers

Zubair

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I see how the wording gets in the way.

I think the wider concept is "bus architectures" be it for computer systems or comms and the case of those implemented in fpga I will view them as a subset connecting various peripherals and processor utilising existing fabric or dedicated routing.

I only used SOPC in 2001 at its early stages and all I knew it was using Avalon bus which is a basic standardised bus system. I don't know what type of switches were used (partial or full buffered crossbar). So I assume that was the beginning of its history in FPGAs.

And yes Avalon bus is the most basic bus architecture for peripherals. Others include AHB, AMBA, USB, etc.

Again I Googled accordingly and noted several altera docs giving description but no figures as you noticed.

But for some other vendors of bus systems here is a link that gives figures:

http://www.ee.ic.ac.uk/pcheung/teaching/ee3_dsd/topic%2010%20-%20handouts.pdf

Thank-you. I really liked what looked like a draft chapter from a book at the end.

It would be a difficult and interesting comparison indeed.

I'll post here if I find anything on the topic.

Cheers

Zubair

I was searching an altera specific comparison. But a generic search immediately gave a good result.

http://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html

Cheers,

Zubair