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Hmm. I'll try to reword my question.
My question is about the interconnect structure between IP cores within one FPGA.
According to the SOPC builder handbook, the SOPC uses a buffered crossbar to connect the IP cores.
Qsys using a network on chip style to connect IP cores.
What did people use before SOPC builder came around with its buffered crossbar interconnect?
And is there any benchmark as to how fast/better these interconnects are compared to each other? Wherever I look, I find high bandwidth low latency etc.. But no real figures..
Hope its clear.
Cheers
Zubair
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I see how the wording gets in the way.
I think the wider concept is "bus architectures" be it for computer systems or comms and the case of those implemented in fpga I will view them as a subset connecting various peripherals and processor utilising existing fabric or dedicated routing.
I only used SOPC in 2001 at its early stages and all I knew it was using Avalon bus which is a basic standardised bus system. I don't know what type of switches were used (partial or full buffered crossbar). So I assume that was the beginning of its history in FPGAs.
And yes Avalon bus is the most basic bus architecture for peripherals. Others include AHB, AMBA, USB, etc.
Again I Googled accordingly and noted several altera docs giving description but no figures as you noticed.
But for some other vendors of bus systems here is a link that gives figures:
http://www.ee.ic.ac.uk/pcheung/teaching/ee3_dsd/topic%2010%20-%20handouts.pdf
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