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Hi,
I was researching around the domain and I would like to ask some expert a question that Google couldn't help me with.
:)
I was trying to trace the interconnect structures and their max data rates. To the best of my knowledge,
Avalon bus came. Then the SOPC interconnect(Buffered crossbar). Then comes Qsys with a network on chip interconnect.
I'm not too sure if there was a thing such as Avalon bus. At the moment, it seems Avalon is an interface specification.
But a few old app notes pointed to an Avalon bus as well.
People came up with bus architectures for connecting IP cores. I could find an article from 2000
http://eetimes.com/electronics-news/4112809/altera-xilinx-hop-on-diverging-buses-in-soc-plans What I would like to know:
A short history lesson on the progression of interconnect technology.
And if there are some speed comparisons anywhere or if anyone has rough figures in his head even.
Pretty sure Qsys with its NOC would be the best. But I'm not sure atm.
Thanks
Cheers
Zubair
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Do you mean interconnect within one fpga or that between several chips.
In either case it looks like a topic for fpga makers area of focus rather than fpga field users.
I just Googled "fpga interconnect technology" and hope this link may help:
http://async.org.uk/tech-reports/ncl-eece-msd-tr-2009-145.pdf If you mean internal fpga interconnect then I don't see Avalon bus as being relevant.
Honored Contributor
