high-speed Serial ADC interface with Cyclone II

hi, have anyone made some design with the High-speed Serial ADC and Cyclone II FPGA?

i am in one project, which adopts Cyclone II FPGA to interface with some 12-bit, 40 MSPS ADCs. While personally, i think it's not a easy task. After completing the deserializer code, the next step is to properly fit the design into the target FPGA. The necessary and critical point is to setup the timing models for STA, and specify the SDC file. Usually how do you consider the constraint of Bit clock and Frame clock?

hopes to listen your suggestions and idea.

regards,

eric