Altera_ForumHonored Contributor16 years agoHigh Level, Low Level, stratix II. I have a data signal with low voltage peak to peak (only 0.5 volts). I want my stratix II FPGA to understand it as a zero and one. To do that I tried changing my input from 3.3v to 1.5, but qu...Show More
Altera_ForumHonored Contributor16 years agoYes, Stratix II LVDS common mode range is said in the datasheet to start from 200 mV.
Recent DiscussionsPower-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) DevicesRegarding Power-Up Sequence for Agilex 5Cyclone V SoC 5CSXC6 Series GXB Utilization and LimitationsHow to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?Agilex 3 PLL in Source Synchronous mode ?