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Altera_Forum's avatar
Altera_Forum
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9 years ago

High fan-out signal

Hello;

After compiling my design in qurtusII, I found this signal "clk~inputclkctrl" have a high fan out. the node"clk" is the clk signal in my design. what can I do to solve this problem.

Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    this signal "clk~inputclkctrl" have a high fan out (...) what can I do to solve this problem

    --- Quote End ---

    Is this a problem at all ?

    As far as I know, clocks need to have the ability to drive signal for a large amount of devices.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Quartus knows about high fanout for clocks and will insert additional logic as needed to compensate for it. You don't need to do anything in most cases.