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Honored Contributor
Honored ContributorHigh fan-out signal
Hello; After compiling my design in qurtusII, I found this signal "clk~inputclkctrl" have a high fan out. the node"clk" is the clk signal in my design. what can I do to solve this problem. Thank...
Altera_ForumHonored Contributor
Honored ContributorQuartus knows about high fanout for clocks and will insert additional logic as needed to compensate for it. You don't need to do anything in most cases.
