help with code

hey guys,

I am new at working with altera. I am learning to write code in vhdl at this moment. I have an assignment due tomorrow and I am having trouble with it. There is an error in my code and I cant figure out what it is. It show the following:

Error (10500): VHDL syntax error at counter.vhd(49) near text "process"; expecting "if"

This is my code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity counter is

port(clk :in std_logic;

start :in std_logic;

mode :in std_logic;

count :buffer integer range 0 to 120;

abcdefghijklmn :out std_logic_vector(13 downto 0));

end counter;

architecture engine of counter is

signal go :std_logic := '0';

signal sel :std_logic;

begin

process(start)

begin

if(start'event and start = '1')then

go <= '1';

end if;

end process;

process(count)

begin

if (count = 0) then

sel <= mode;

end if;

end process;

process(go,count,clk,sel)

begin

if ((go = '0') or (count > 60)) then

count <= 0;

else if ((go = '1') and (clk'event and clk = '1')) then

if (sel = '0') then

count <= count + 5;

else

count <= count + 12;

end if;

end if;

end process;

end engine;