Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThere are few other changes I made here:
always @(negedge clk) begin : FSM // finite state machine case (state) hold : begin if (count<63) // setting states for downsampling state <= hold; else state <=sample; end default: state <= hold; endcase end assign sx={{16{x[7]}},x_in}; // Integrator always @(posedge clk or reset)begin if(reset) begin count = 6'd0; x = 8'd0; i0 = 24'd0; i1 = 19'd0; i2 = 14'd0; end begin: I x <= x_in; i0 <= i0 + {{16{x[7]}},x_in}; //sx; i1 <= i1+i0[23:7]; i2 <= i2+i1[18:5]; case (state) //downsample sample : begin c0 <= i2[13:1]; count <= 0; //reset counter once a sample has been fetched end default : count <= count+1; endcase end end // COMB always @(posedge clk) begin: COMB i2d1 <= c0; c1 <= c0-i2d1; c1d1 <= c1[11:1]; c2 <= c1[11:1]-c1d1; c2d1 <= c2[10:1]; c3 <= c2[10:1]-c2d1; end assign y_out=c3[9:2]; endmodule