Help with CIC decimation filter

Now that I have 5 posts, let me post the code and the simulation properly:

// cic decimation filter : R=64, M=1, N=3
module cicdecim64 (x_in,y_out,clk,reset);
input                    clk,reset;
input             x_in;
output             y_out;
parameter hold=0, sample=1;
reg                    state;             //sample or hold states
reg                count;            //count till 63 starting from 0
reg                x;                    //input
wire            sx;                //sign extended input
reg             i0;        //Integrator output section 0
reg             i1;        //output section 1 under the consideration of Haugenauer's pruning
reg             i2;
reg              i2d1, c1, c0; // Integrator+COMB 0
reg             c1d1, c2;
reg              c2d1, c3;
always @(negedge clk)
begin : FSM                      // finite state machine
case (state)
hold : begin
if (count<63)                     // setting states for downsampling
state <= hold; 
else
state <=sample;
end
default:
state <= hold;
endcase
end
assign sx={{16{x}},x_in};
// Integrator
always @(posedge clk)begin
if(reset) begin
i0 <= 24'd0;
i1 <= 19'd0;
i2 <= 14'd0;
x  <= 8'd0;
end
else
x  <= x_in;    
i0 <= i0+sx;
i1 <= i1+i0;
i2 <= i2+i1;
case (state)                     //downsample
sample : begin
c0 <= i2;
count <= 0;                        //reset counter once a sample has been fetched
end
default :
count <= count+1;
endcase
end
// COMB
always @(posedge clk)
begin: COMB
i2d1 <= c0;                        
c1   <= c0-i2d1;
c1d1 <= c1;                
c2   <= c1-c1d1;
c2d1 <= c2;
c3   <= c2-c2d1;
end
assign y_out=c3;
endmodule

`timescale 1ns/1ps
module test;
reg                clk,reset;
reg         x;
wire             y;
cicdecim64 cic (x,y,clk,reset);
initial begin
x <=8'd1;
clk<=1'b0;
reset <= 1'b0;# 4 reset=~reset;# 5 reset=~reset;
end
always# 4 clk=~clk;
endmodule